Semiconductor memory devices are becoming more and more complex as their size decreases and their storage density increases. To help handle some of the increase in storage density, an architecture comprising multiple subarrays of memory cells for storing values has been adopted in dynamic random access memory (DRAM) devices. Each of the subarrays comprises multiple columns and multiple rows of memory cells. Rows are accessed or "fired" by activation of row address signals. Each column of memory cells in a subarray is coupled to a sense amplifier which in turn is selectively coupled to pairs of I/O lines which are local to each subarray. Sense amplifiers may be coupled to columns of cells in more than one subarray. Multiplexors in gaps between subarrays are used to couple local I/O lines to pairs of global I/O lines, which provide the values for several of the subarrays.
During normal memory operation, the multiplexors are often controlled by a signal that is active only if a row has been fired in that subarray. There are multiple global I/O lines, each one providing data from multiple subarrays. The multiplexors allow only one cell to be coupled through a local I/O line to a global I/O line to prevent conflicting signals from occurring on the global I/O lines. Hence, the control of the multiplexors is tied closely to row decode signals.
This type of architecture has been very helpful in obtaining DRAMs beyond the 16 MB generation. However, as the storage capacity has increased, so have testing times. The same architecture that facilitates higher storage capacities, has also made it time consuming to test the DRAMs by limiting the number of rows that can be fired at any one time. In one type of row disturb test, a row is first written with data, and then accessed or fired and latched as many times as possible during a standard refresh cycle. This simulates a worst case condition to which a customer could subject the DRAM. It may result in rows adjacent to the fired row being affected by noise or leakage mechanisms between the rows. Following this type of test, other data cells, such as those in nearby rows are read to see if they have been affected by the row disturb. When the array comprises an eight by eight subarray arrangement, only the rows of a block of eight subarrays may be fired during this test. That means that the test must be repeated for each row in the subarrays multiplied by eight more subarrays. With 512 rows per subarray, the test is done 8096 times. The time taken just to fire the rows is then 8096 times the refresh rate. This type of testing is usually performed both at the wafer level, and at the final package level at least twice. The large amount of time to test the DRAM requires additional resources per DRAM which increases the cost of the DRAMs.
There is a need to cut down the time it takes to perform row disturb types of testing. There is a need to cut down such time without adding complex circuitry to the DRAM device, which could cut achievable densities. There is yet a further need to reduce the expense associated with testing of DRAM devices.